This invention generally involves a method for manufacturing shallow trench isolation (STI) structures in semiconductor device manufacturing and more particularly to a method for reducing divot formation at trench corners during an etching process.
In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Every device on the chip must be electrically isolated to ensure that it operates independently without interfering with another. The art of isolating semiconductor devices has become an important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper electrical isolation among devices will cause current leakage, and the current leakage can consume a significant amount of power as well as compromise functionality. Among some examples of reduced functionality include latch-up, which can damage the circuit temporarily or permanently, noise margin degradation, voltage shift and cross-talk.
Shallow trench isolation (STI), is the preferred electrical isolation technique especially for a semiconductor chip with high integration. Broadly speaking, conventional methods of producing a shallow trench isolation feature include: forming a hard mask over the targeted trench layer, patterning a soft mask over the hard mask, etching the hard mask through the soft mask to form a patterned hard mask, and thereafter etching the targeted trench layer to form the shallow trench isolation feature. Subsequently, the soft mask is removed (e.g., stripped) and the shallow trench isolation feature is back-filled with a dielectric material.
In the STI technique, the shallow trench isolation area is first defined to form isolation trenches surrounded by areas of wafer having a pad oxide layer and a polish-stop nitride layer on the surface. The isolation trench is then thermally oxidized to form a thin oxide layer on the isolation trench surfaces. A thin nitride liner is often first deposited inside the isolation trench surfaces to prevent stress during the subsequent oxidation steps because the stress causes dislocations in the silicon wafer. The isolation trench is then filled with a chemical vapor deposited (CVD) oxide and chemically mechanically polished (CMP) back to the polish-stop nitride layer to form a planar surface. The polish-stop nitride layer is then removed. At this time, if there is a nitride liner, exposed areas of the nitride liner are etched back as well, creating a divot (depression). If there is no nitride liner, a divot can still form in the SiO2 surface adjacent to the Silicon due to stress at the SiO2 interface. The pad oxide is then removed by a wet etch, usually hydrofluoric acid (HF), which may also cause the divot to grow further. The formation of such divots may affect the electrical integrity of semiconductor devices in a number of ways such as, example, altering the threshold voltage of a field effect transistor (FET).
Referring to FIG. 1, which shows a cross-sectional view of a typical trench isolation structure 10 during a stage of an STI process, it can be seen that divots (depressions or voids) form at the corners 12 of the trench due to preferential etching away of an oxide trench liner material 18 following a hydrofluoric acid (HF) treatment. The HF treatment is typically used to remove a pad oxide layer (not shown) overlying the silicon substrate 14 after removing the polish stop nitride layer overlying the pad oxide layer (not shown). Typically the oxide trench liner 18 material is deposited inside the trench following trench formation. The oxide trench liner 18 layer serves several purposes including reducing stress in the semiconductor substrate 14 induced when forming the trench, provides some minimal rounding of the trench corners, and some protection against divot formation during a planarization procedure to remove excess trench filling material. The trench corners however, are particularly susceptible to defects induced by stress and are likewise more susceptible to form divot formation, as shown at 12, when subjected to wet etching processes with, for example, hydrofluoric acid (HF).
In order to solve problems related to divot formation in general, methods have been suggested, for example, where an oxide spacer is formed after the polish stop nitride layer is removed. However, problems still occur when using the oxide spacer because there is no etch stop and it is possible to damage the underlying silicon wafer during the reactive ion etch (RIE) process used to form the oxide spacer. Additionally, if the oxide spacer is too thin, it may be completely removed during the subsequent wet etches and divots may form.
P. C. Fazan, et al., propose a method for eliminating the corner effects in U.S. Pat. No. 5,433,794 entitled xe2x80x9cSPACERS USED TO FORM ISOLATION TRENCHES WITH IMPROVED CORNERSxe2x80x9d. They create a smooth trench profile with a self-aligned cap or dome. The isolating material is deposited extending over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.
More recently, another method has been proposed to solve the problem of divot formation in general, using spacer formation. In U.S. Pat. No. 5,923,991, Bronner et al. propose the use of a spacer, similar to that suggested by Fazan et al. The spacer is of a material that is etched selectively to silicon dioxide during a reactive ion etch process and additionally has a low etch rate in hydrofluoric acid (HF). According to this method, the trenches are lined with thermally grown oxide followed by a liner of silicon nitride. The trenches are then completely filled with a chemical vapor deposited silicon dioxide. The silicon nitride layer is then removed selectively to the oxide which forms divots. Next, a spacer material with low etch rates to hydrofluoric acid (HF) solutions is deposited over the entire surface. The spacer material is then reactive ion etched (RIE) directionally to form spacers adjacent the edges of the silicon dioxide trench-filling material that have not been planarized. Although the silicon nitride liner is still etched during the initial silicon nitride polish stop removal step, the spacers will protect the silicon dioxide next to the etched liner during the subsequent wet etches, which are performed to remove the pad oxide and planarize the surface.
However, what is needed is a process with fewer processing steps with protective layering providing more effective protection against divot formation, especially at trench corners which may be more susceptible to material removal (divot formation) during wet etches, with for example, hydrofluoric acid (HF).
It is therefore an object of the invention to provide a method of protecting trench corners in a shallow trench isolation process (STI) from divot formation during wet etches with, for example, hydrofluoric acid (HF).
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for minimizing divot formation in a shallow trench isolation process.
According to a first embodiment, the present invention provides a method for minimizing divot including providing a substrate including a silicon substrate with a pad oxide layer formed over the silicon substrate and a nitride layer formed over the pad oxide layer and a trench opening extending through said nitride layer and pad oxide layer into the silicon substrate; growing a liner oxide material conformally over a portion of the trench opening extending into the silicon substrate; removing the liner oxide material including forming at least one recession adjacent the trench opening by removing a portion of the pad oxide layer adjacent to the trench opening; and, conformally depositing an etching resistant layer having an etch rate lower than a silicon oxide etch rate over the nitride layer including the trench opening extending through said nitride layer and pad oxide layer into the silicon substrate.
In related embodiments the etching process includes the use of a hydrofluoric acid solution. Further, the pad oxide layer includes silicon oxide. Further yet, the nitride layer includes silicon nitride. Further yet, the liner oxide includes silicon oxide. Further yet, the etching resistant layer is selected from the group consisting of silicon nitride, silicon oxynitride, and titanium nitride.
In yet a further related embodiment, the method according to the present invention includes removing the liner oxide material to include removing at least a portion of the pad oxide material extending about 200 Angstroms to about 1000 Angstroms in a direction substantially parallel to a silicon substrate surface adjacent to the trench opening. Further, the etching resistant layer is conformally deposited over the at least one recession to form a collar over corners defining the trench opening.
Related embodiments are presented that will be become clear as presented below in the Detailed Description and as further defined by the associated claims.